1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly to a cell structure of a DRAM (Dynamic Random Access read and write Memory) using a thin film transistor.
2. Description of the Related Art PA1 a semiconductor substrate of a first conductivity type; PA1 a first insulation film formed on a surface of the semiconductor substrate; PA1 a gate electrode formed on the first insulation film; PA1 a second insulation film formed on the first insulation film and the gate electrode; PA1 a cylindrical gate insulation film formed on a surface of the gate electrode which is exposed in a trench formed to extend through the second insulation film, the gate electrode and the first insulation film to an interior of the semiconductor substrate; PA1 a capacitor insulation film formed on a surface of the semiconductor substrate which is exposed in the trench; PA1 a cylindrical conductive film including a region doped with an impurity of the first conductivity type and formed on the gate insulation film, a region doped with an impurity of a second conductivity type and formed on a surface of the second insulation film which is exposed in the trench and a region doped with an impurity of the second conductivity type and formed on the capacitor insulation film; and PA1 a conductive column formed in a region surrounded by the cylindrical conductive film. PA1 a semiconductor substrate of a first conductivity type; PA1 a first insulation film formed on a surface of the semiconductor substrate; PA1 a gate electrode formed on the first insulation film; PA1 a second insulation film formed on the first insulation film and the gate electrode; PA1 a cylindrical gate insulation film formed on a surface of the gate electrode which is exposed in a trench formed to extend through the second insulation film, the gate electrode and the first insulation film to an interior of the semiconductor substrate; PA1 a capacitor insulation film formed on a surface of the semiconductor substrate which is exposed in the trench; PA1 a cylindrical conductive film including a region doped with an impurity of the first conductivity type and formed on the gate insulation film, a region doped with an impurity of a second conductivity type and formed on a surface of the second insulation film which is exposed in the trench and a region doped with an impurity of the second conductivity type and formed on the capacitor insulation film; PA1 a cylindrical third insulation film formed on an inner surface of the cylindrical conductive film; and PA1 a conductive column formed in a region surrounded by the cylindrical third insulation film.
In recent years, the demand for greater integration of semiconductor devices has been increasing, as the devices become more and more refined in size and detail.
To meet the demand, a so-called ring channel TFT (Thin Film Transistor) having a cylindrical channel region has been proposed. FIG. 1A shows a longitudinal cross-sectional view of a conventional ring channel TFT. A cylindrical conductive layer 1 is formed of doped Si. The interior of the cylindrical conductive film is hollow. It is possible for the interior to be filled with a silicon oxide film (not shown). In the conductive film 1, a channel region 1b doped with a P-type impurity is formed between an N-type drain region 1a and an N-type source region 1c.
FIG. 1B is a cross sectional view of the cylindrical channel region taken along the line 1B--1B of FIG. 1A. As shown in FIG. 1B, a gate insulation film 2 and a ring-shaped gate electrode 3 made of conductive polycrystalline silicon are formed in this order on the outer surface of the cylindrical channel region lb.
FIGS. 2A to 2C show the cell structure of a DRAM containing the conventional ring channel TFT shown in FIGS. 1A and 1B.
As shown in FIG. 2A, a first insulation film 6 is formed on a surface of a P-type silicon substrate 5. A gate electrode 3, having a predetermined pattern, is formed on the first insulation film 6 and serves as a word line. A second insulation film 7 is formed on the gate electrode 3 and the first insulation film 6. A gate insulation film 2 is formed inside the trench 8 formed to a predetermined depth in the substrate 5 so as to cover the gate electrode 3. A capacitor insulation film 9 is formed on a side wall of the trench 8 in the substrate.
A doped Si film 1 is continuously formed on an upper surface of the second insulation film 7 and an inner surface of the trench 8. A hollow portion remains in the trench 8, but can be filed with a silicon oxide film (not shown), if necessary.
A region 1b of the doped Si film 1, which is formed on the gate insulation film 2, is doped with a P-type impurity and serves as a channel. The other portion of the doped Si film 1 is doped with an N-type impurity. An upper portion of the doped Si film above the channel region 1b is a drain region la and a lower portion of the doped Si film under the channel region 1b is a source region 1c.
A region 1e of the doped Si film 1, which is formed on the second insulation film 7, serves as a bit line. The portion of the source region 1c, which is in contact with the capacitor insulation film 9, serves as a charge storage layer. An N.sup.+ region 10 is formed under the trench 8 in the substrate.
FIGS. 2B and 2C are cross-sectional views of the DRAM shown in FIG. 2A, taken along the lines 2B--2B and 2C--2C, respectively. As shown in FIG. 2B, the gate insulation film 2 and the gate electrode 3 are formed on the outer surface of the cylindrical channel region in this order in a cross section including the channel region 1b. As shown in FIG. 2C, the capacitor insulation film 9 covers an outer surface of a charge storage layer 1d.
The gate electrode 3, the gate insulation film 2, the channel region 1b, the drain region la and the source region 1c constitute a ring channel TFT 11. The silicon substrate 5, the capacitor insulation film 9 and the charge storage layer 1d constitute a cell capacitor 12.
FIG. 3 shows an equivalent circuit of the DRAM shown in FIG. 2. The word line 3 is electrically connected to a gate electrode of the ring channel TFT 11. Drain and source regions of the ring channel TFT 11 are electrically connected to the bit line 1e and the charge storage layer 1d of the cell capacitor 12, respectively.
As described above, in the conventional ring channel TFT, the channel region is in contact with only the gate insulation film on the outer periphery thereof and the drain and the source regions formed in an upper level and in a lower level of the channel region. For this reason, it is difficult to apply a back gate bias to the channel region and a sufficient cut-off characteristic cannot be obtained.
Further, in the DRAM having the conventional ring channel TFT, it is difficult to obtain a sufficient capacitance by means of the capacitor 12 comprised of the silicon substrate 5, the capacitor insulation film 9 and the charge storage layer 1d.